Totalview® for HPC Reference Guide : PART IV Platforms and Operating Systems : Chapter 11 Architectures : ARM64 : ARM64 FPCR Register
ARM64 FPCR Register
For your convenience, TotalView interprets the bit settings of the ARM64 FPCR register. You can edit the value of the FPCR and set it to any of the bit settings outlined in the following table.
Value
Bit setting
Meaning
0x100
IOE
Invalid operation exception enable
0x200
DZE
Division by zero exception enable
0x400
OFE
Overflow exception enable
0x800
UFE
Underflow exception enable
0x1000
IXE
Inexact exception enable
0x8000
IDE
Input denormal exception enable
0x0 (bits 23 and 24 clear)
RMode=RN
Round to nearest
0x400000
RMode=RP
Round towards plus infinity
0x800000
RMode=RM
Round towards minus infinity
0xC00000
RMode=RZ
Round towards zero
0x1000000
RMode=(per above)+FZ
Flush-to-zero
0x2000000
RMode=(per above)+DN
Operations on NaN return default NaN
0x1000000
RMode=(per above)+AHP
Alternative half-precision